Homayoun Shahri, PhD

32732 Ballena Dana Point, CA 92629

Tel: 949-388-7100

Cell: 949-436-2127

homayoun@tufon.com

www.tufon.com

 

Summary:

         24+ years of industrial, academic, and management experience in Information Theory, Multimedia, Security, cryptographic systems and architectures, Communications Systems, and Software Engineering for embedded systems.

         One of the founding members of Malleable Technologies (acquired by PMC-Sierra).

         10+ years of experience, at various startups.

         Expertise in Channel/Source coding, Encryption/Decryption algorithms and software/hardware implementations, Modulation, Digital Signal Processing, Image/Video/Speech/Audio Coding, Software Engineering, and Firmware Development.

         Designed a novel programmable architecture, based on programmable data paths, targeted for implementing Cryptographic algorithms.

         Participated in the Design of various sections of MDP (Malleable Data Path, at Malleable Technologies). Managed the applications development group at Malleable/PMC-Sierra.

         Designed and Implemented new algorithms for channel coding, video teleconferencing, image compression, and speech enhancements (blind noise reduction algorithms).

         Implemented, in fixed point arithmetic, standards based lossy/lossless image/speech/audio/video compression algorithms on embedded platforms (MPEG Layers 2, and 3, WMA, MPEG-4, and H.264).

         Software engineering (C, C++, Java, assembly, scripting languages), DSP implementation, behavioral modeling (Verilog, and SystemC), Android development. Strong embedded software development on embedded Linux, Expertise in Linux OS.

         Expertise in various DSPs and embedded processors, including ARM cortex A8 and A9, Tensilica, Equator MAP-15, QDSP6.

         20+ published papers in refereed Journals and Conferences. Several issued and pending patents.

         Senior member, IEEE.

         Adjunct Professor of Electrical Engineering (Digital Signal Processing), University of Southern California (USC), and Lecturer (Cryptography) at UC-Irvine Extension program.

 

 

 

 

 

 

Experience:

 

Oct 2006 -Present

Principal Engineer, Qualcomm Incorporated, San Diego, CA

         Leading multimedia competitive analysis within QCT.

         Developed an adnroid app which on the surface displays percentage of the battery left, and predicts battery life. Underneath, this android app collects various information such as which activity has the UI focus, the length of time the activity is running, battery usage, CPU usage, temperature of the device, etc. This information is transmitted anonymously to a server on daily basis, and is used to study consumer behavior and usage of smart phones. The outcome of this study is expected to result in more fine tuned and optimized apps, as well as pointing to strategies and optimizations to increase the battery life of the device.

         Led the effort to analyze collected consumer data (2000 respondents) resulting in clusters of users and usage patterns of smart phones.

         Leading efforts to identify cause and reduce power consumption on QCOM based phones.

         Designed a novel (near end blind) noise reduction algorithm for cell phone receive path (patent filed).

         Designed the DC-blocking filter for all the recent QCOM's audio codecs.

         Led the design/development of Audio Front End (AFE), which is going to be based on Component Services (CS), and will distributed across ARM, QDSP6 processors.

         Helped our Camera team with CS concept, and designed and provided an algorithm for fixed rate coding of JPEG, and participated in the design of a multi-threaded implementation of JPEG.

         Developed expertise in QDSP6 architecture, and programming, as well as the internally developed RTOS used on this processor (Qube)

         Developed expertise in Component Services and OpenMM, and conducted two training sessions for colleagues in the organization.

         Have completed internal trainings in: ARM MP architecture and design for cortex A8 and A9, Multiprocessor SW design, Advanced communications, LTE, Verilog (Basic, and Advanced), FPGA design and synthesis,

June 2006 -Oct 2006

Consultant, Quartics Inc, Irvine, CA

         Implemented a functional simulator for Quartics's VLIW architecture. Modified the assembly language of Quartics's processor so that code can be written in 'C' syntax, and can be compiled with a C-compiler, thus providing very fast speed, and performance.

         Implemented the Motion Compensation block for AVC/AVS/VC1 codecs. This bit-exact implementation was used for hardware verification purposes.

Dec 2003 -June 2006

Consultant/Staff Scientist, MediaWorks Integrated Systems Inc, Irvine, CA

         Managed the Media group, through successful release of MW-301.

         Implemented Windows Media DRM-10 on MediaWorks' programmable processors.

         Implemented and partitioned H.264 Encoder to run in a heterogeneous environment. Worked on definition and design of new Tensilica Instruction Extensions (TIE) instructions for HD resolution (720p, and 1080p) video encoding. Implemented CABAC, and worked on defining TIE instructions to speed up CABAC encoding and decoding.

         Implemented WMA-9 decoder on MediaWorks' programmable architecture.

         Implemented MP3 decoder on MediaWorks' programmable architecture.

         Implemented the inner loops of Windows Media Video (WMV-9) main profile.

         Implemented JPEG on the the Tensilica processors (Xtensa), taking advantage of the TIE instructions running on 4 processors in parallel. Added hooks to the compressed JPEG header to facilitate parallel decoding.

         Worked on and ported Mpeg-4 video (D1 resolution) encoder to Tensilica processors, running on 4 processors in parallel. Participated in defining TIE instructions for video compression. Hand optimized many inner loops, by assembly coding or algorithmic modifications. Defined the memory map for the encoder, as well as the I/O and DMA requirements. Defined memory partitioning for the Mpeg-4 encoder. Optimized various MIPS intensive parts of Mpeg-4 decoder.

         Worked on device drivers, hardware verification, audio, and video compression in an embedded environment. Implemented a Nand Flash device driver, and verified the the operation of the Nand Flash Controller.

Jan 2003 -May 2005

Adjunct Professor, University of Southern California (USC)

         Taught an advance course in "Digital Signal Processing" (DSP).

2003 - 2006

Lecturer, University of California Irvine, Extension Program (UCI)

         Taught "Theory and Applications of Cryptography in Network and Computer Security".

Oct - Dec2003

Consultant,GenGears Inc, Irvine, CA

         Designed and implemented a streaming protocol for streaming MP3 encoded audio over 802.11b. Implemented the MP3 transmitter and receiver. The design received the encoded audio, decoded, and played the audio, in an embedded Linux environment.

Sept - Oct2003

Consultant, Pacific Digital Corporation, Irvine, CA

         Designed and implemented a protocol for discovering the IP addresses of attached devices running embedded Linux connected across heterogeneous networks. Designed and implemented a protocol for authentication, identification, and encryption of transmitted data to the devices connected across a heterogeneous network.

Nov 2002 -Sept 2003

Consultant, Equator Technologies, Campbell, CA

         Implemented MPEG Audio Layers II and III (MP3). Converted the standard code from floating to fixed point. Modified the Psycho Acoustic (PA) model to enhance the performance. Optimized and ported the code to the Equator BSP-15 Processor. Converted and ported Windows Media Encoder (Audio-WMA) to fixed point (from floating point) and optimized the code for BSP-15 Processor. Modified the algorithm so that a MIPS target is met, with little perceptual difference.

Apr 2002 - Mar 2003

Consultant, Plexus Networks, San Jose, CA

         Designed and implemented an accurate channel model in C++ which incorporates both multi-path, as well as memory. Also worked on various communications related algorithms. Implemented fractionally spaced and decision feedback equalizers targeted for the optical channel (to correct PMD and other artifacts).

Feb - Sept 2002

Consultant, Caveolan, Irvine, CA

         Designed (and implemented in Verilog) an AES core, which resulted in one of the most efficient (speed and area) designs in the industry. Worked on the design of a novel programmable processor for encryption and decryption. The design includes high level architecture design, hardware/software partitioning, high level system level design, I/O, cycle accurate simulator (C++), and simulation in an FPGA, as well as overall system security.

Jan - Dec2002

Consultant, Teramedia Communications, La Jolla, CA

         Worked on the specifications and implementation (C, and C++) of a system for transmission of various media types (including speech, text, and graphics) embedded in MPEG transport as well as analog VBI for Scientific Atlanta set top applications.

July - Dec 2001

Consultant, Valence Semiconductor, Irvine, CA

         Worked on performance evaluation of Valence's Security Processor (VSP), as well as developing specs for VxWorks/Linux ARM-9 drivers for VSP.

         Worked on the design and implementation of a novel architecture for distributing video in the home environment, using wire-line as well as wireless technologies

         Evaluated various DSP cores for use in Valence products.

         Coordinated R&D team efforts across various satellite locations of Valence.

Jan - Apr 2001

Consultant, Ikanos Communications, Fremont, CA

         Implemented systematic Reed-Solomon encoders based on a parallel approach, and decoding based on an inversion-less Berlekamp-Massey algorithm. Also implemented a soft decision decoder for Reed-Solomon codes.

         Worked on implementation of Parallel Concatenated Turbo Codes, for a contribution to T1/E1 sub-committee on G.DMT-BIS.

         Consulted on the applications and implementations of Voice Over Packet, as well as various applications such as packet classifications on Ikanos's processor.

Mar 1998 - Dec 2000

Director, Applications Development, Malleable Technologies, San Jose, CA Manager, DSP Development, PMC-Sierra, Santa Clara, CA.

         One of the founding members of Malleable Technologies (Malleable Technologies, was acquired by PMC-Sierra, June, 2000).

         Formed and managed the Firmware group. (Hired 21 engineers and first level managers. Also managed outside contractors in various parts of the country)

         Defined various parts of MDP (Malleable Data Path programmable processor). Defined many of the internal resources of the MDP based on the target applications' resource requirements, i.e. register file size, instruction memory, application specific instructions, efficient address generation, etc.

         Helped in defining the development tools for MDP, including cycle accurate simulator, assembler, and MDP assembly language, GUI-debugger, C-compiler extensions.

         Analyzed complex speech coders, communications blocks, such as QAM Mod/Demod, RS-en/decoders, Viterbi decoders, as well as various other complex signal processing algorithms to estimate the MIPS/Resource requirements on MDP (Malleable Data Path).

         Helped in defining Malleable's Voice Over Packet products' requirements. This includes both VoIP and VoATM products.

         Managed and conducted training sessions on the architecture and programming of MDP for our external customers.

         Designed and implemented various Comm/DSP/Speech Coding, and Channel coding algorithms on MDP

         Implemented a video server for Video On Demand (VOD), which included development of a Windows NT device driver, and a multi-threaded client-server host application, including a conditional access server (used for crypto key exchange). This work was carried out for an early customer and investor in Malleable (DIVA-TV).

1996-1998

Principal Engineer, Liberate Technologies/NCI/Navio Communications, Redwood Shores, CA.

         Implemented a new lossy image compression scheme (XNG) suitable for set top boxes with limited computation power (less than 30 mips), used in NCI's DTV Navigator. XNG's compression algorithm is based on a hybrid transform-subband coding scheme. No multiplication is required in the decoder. XNG produces JPEG like quality images at a fraction of decoding complexity of JPEG. Also implemented the lossless version of XNG which is based on ZLIB compression for synthetic and animated images. XNG encoder is used on servers to transcode different image formats to XNG. The decoder is used in set top boxes with limited memory and CPU cycles. Developed a Netscape Plugin to view XNG compressed files on PCs.

         Implemented Server side (Proxy) transcoders for Audio and Image compression for NCI's DTV Navigator. The transcoders handle GIF/PNG/JPEG/WAV/AIFF/WAV formats.

         Implemented GSM speech coder and voice activity detector (VAD) for IP telephony on NCI's TV Navigator product. This was an variation of Netscape CoolTalk.

         Worked on definition and design of a Channel Coding for Intel's InterCastTM(jointly with Intel and Microsoft).

         Ported existing data/image/speech/audio compression algorithms to NCI's (Liberate Technologies) embedded platform.

1996

Principal DSP Engineer, Microunity Systems Engineering, Sunnyvale, CA.

         Worked on implementation of Cable Data Modem on Microunity's Media Processor.

         Designed and Implemented division-less systematic encoders/decoders for Reed-Solomon codes using parallel group instructions for Microunity's processors.

1990-1996

Principal Member of Technical Staff, AT&T Bell Laboratories, Murray Hill, NJ.

         Developed (jointly with Jont Allen) a network (telephone) based low cost, low complexity transmitted noise reduction (TNR) scheme. The developed algorithm is robust with respect to different types of background noise and performs very well in severely noisy conditions. Our novel approach is based on syllabic expansion and is implemented using "short time Fourier analysis/synthesis".

         Researched and developed (jointly with Ingrid Daubechies) a wavelet-based TNR algorithm for possible use in the network and/or cellular systems. This algorithm could be integrated in the wavelet-based speech coders with very little added complexity.

         Developed and designed a method for remotely turning TrueVoiceSM off in the long distance network. This is deemed necessary in situations where there is a possibility of multiple speech enhancements.

         Designed a DCT based video coder using trellis-based structured vector quantizer (TBSVQ). This is a fixed-rate quantizer which is known to achieve the boundary gain (shaping gain in modulation) and a significant portion of the granular gain (coding gain in modulation) asymptotically.

         Worked on video coding schemes, specifically subband and DCT- based coders for teleconferencing applications. Our subband-based coder was implemented in both 2-D combined with motion compensation and 3- D. The goal of this project was to exploit the human visual system (HVS) in design of video coders and simultaneously reduce the coding delay. This work resulted in developing a new fast algorithm for motion compensation.

         Designed a high quality 3-D subband video coder which used a distortion minimizing Lloyd-Max quantizer and near entropy run-length coding resulted in reducing the coding delay.

         Worked on various speech enhancement techniques, specifically TrueVoiceSM and their real-time implementations on AT&T and TI digital signal processors, resulting in the first ISDN-based prototype of the TrueVoice effect.

1987-1990

Assistant Professor, EE Department Lafayette College, Easton, PA

         Courses taught include: Digital Signal Processing, Communications Theory, Digital Speech Processing and Synthesis, Coding Theory, Spectral Estimation and Analysis, Introduction to Signals and Systems.

         Developed a software package (GFCALC) written for arithmetic, matrix, polynomial and transform operations over arbitrary Galois Fields of characteristic two.

Skills:

         Fluent in C++, JAVA programming languages, and Verilog; KSH, AWK, PERL JavaScript script languages; HTML, and MATLAB; and Verilog. Detailed knowledge of UNIX and Windows NT/XP operating systems, WIN32 APIs and programming environment. Expertise in Linux OS. Detailed knowledge of TCP/IP, and familiar with ATM AAL1/2/5 protocols, as well as VoIP and I366.2 VoATM protocols. Familiar with several digital signal processors (DSP) including all TI fixed and floating point series, Xtensa, ARM, as well as Xilinx FPGAs.

Education:

         PhD Lehigh University, Bethlehem, PA. (June, 1990) Thesis: On Bounding the Minimum Distance and Decoding of Cyclic Codes.

         MS Lehigh University, Bethlehem, PA. (Aug, 1984) Thesis: On Burst-Error Correcting Capability of Cyclic Codes of Composite Length.

         BE SUNY at Stony Brook, Stony Brook, NY. (June, 1982)

Professional Activities:

         Senior member, IEEE. Member Tau Beta Pi, and Eta Kappa Nu.

Personal:

         U.S. Citizen.

Selected Publications:

         H. Shahri, "Mapping DSP Algorithms to DSP Architectures", Invited paper, published in the ACM Queue Magazine, vol. 2, no. 1, pp. 32-41, March 2004.

         H. Shahri, "The Blurring Lines Between Hardware and Software", Invited paper, published in the ACM Queue Magazine, vol. 1, no. 2, pp. 42-48, April 2003.

         H. Shahri, et. al. "On Parallel implementation of G.975, (255, 239) RS code", presented at the Global Signal Processing Conference, GSPx, Dallas Tx. Mar 2003.

         H. Shahri, et. al. "On Efficient Implementation of Advanced Encryption Standard (AES)", presented at the Global Signal Processing Conference, GSPx, Dallas Tx. Mar 2003.

         Behrooz Rezvani, Dale Smith, Sam Heidari, and Homayoun Shahri, "Method and apparatus for an X-DSL modem supporting multiple X-DSL line codes", patent number 6,959,036, US patent office, awarded 2004 to Ikanos Communications.

         C. Abbott, H. Shahri, "Count/Address Generation Circuitry", patent number 6601158, US patent office, awarded July 2003 to PMC-Sierra.

         H. Shahri, "Comments on Inversionless decoding of both errors and erasures of Reed-Solomon codes", submitted to IEEE Transactions on Communications, Jan. 1999.

         N. Mohsenian, H. Shahri, and N. Nasrabadi, "Scalar Vector Quantization of Medical Images," special issue of IEEE Transactions on Image Processing, vol. 5, no. 2, pp.386-392, Feb. 1996, and in proceedings of the IEEE Int. Conf. on Medical Imaging, San Francisco, CA, Oct. 1995.

         N. Mohsenian and H. Shahri, "MR Image Compression using Scalar Vector Quantization," in proceedings of SPIE conf., Philadelphia, PA, Oct. 1995.

         R. Laroia, H. Shahri and T. Alonso, "On TB-SVQ based Motion Compensated DCT Coding of Video Conference Sequences," in proceedings of Int. Conf. on Image Processing (ICIP), Austin, TX, Nov. 1994.

         R. Laroia, H. Shahri, T. Alonso, "A Fixed Rate Video Coder for Teleconferencing," in proceedings of the Int. Symp. on Information Theory, ISIT, Trondheim, Norway, July, 1994.

         S. Narayanan, H. Shahri, et. al., "Fast and Efficient Techniques for Motion Estimation using Subband Analysis," in proceedings of Int. Conf. on Image Processing (ICIP), Austin, TX, Nov. 1994.

         H. Shahri, et. al., "3-D Subband Coding of Videoconference Sequences," in proceedings of Int. Conf. on Signal Processing Applications and Technology (ICSPAT), Dallas, TX, Oct. 1994.

         G. L. Feng, K. K. Tzeng, and H. Shahri, "A Generalization of the Forney Formula," IEEE Transactions on Information Theory (submitted July 1994).

         H. Shahri, et. al., "Subband Coding of Videoconference Sequences at 384 KBPS," in proceedings of Int. Conf. on Signal Processing Applications and Technology (ICSPAT), Santa Clara, CA, Sept. 1993.

         H. Shahri and J. Hartung, "A 3-D Subband Coder for Teleconferencing at 384 KBPS," in proceedings of the IEEE Int. Symp. on Information Theory, San Antonio, TX, Jan. 1993.

         D. Youtkus, H. Shahri, and M. Luo, "A Low Delay JPEG based Image Coder using a single AT&T DSP32C," in proceedings of Int. Conf. on Signal Processing Applications and Technology (ICSPAT), Boston, MA, Nov. 1992.

         H. Shahri and K. K. Tzeng, "On Error and Erasure Decoding of Cyclic Codes," IEEE transactions on Information Theory, Vol. 38 pp. 489-496, March 1992, and in proceedings of the Int. Symp. on Information Theory, ISIT, San Diego, CA, Jan. 1990.

         H. Shahri, "DFT, Convolution and Error Correcting Codes," in proceedings of the IEEE Int. Conf. on Acoustics, Speech and Signal Processing (ASSP), San Francisco, CA, March 1992.

         H. Shahri, K. K. Tzeng, and J. C. M. Janssen, "On Error and Erasure Decoding of Cyclic Codes upto the Roos Bound," in proceedings of the Int. Symp. on Information Theory, ISIT, Budapest, Hungary, June 1991.

         H. Shahri, K. K. Tzeng, and G. L. Feng, "On Evaluating Errors and Erasures of Cyclic Codes," in proceedings of the Int. Symp.on Information Theory and its Applications, ISITA, Waikiki, Hawaii, Nov. 1990.

         H. Shahri, K. K. Tzeng, and G. L. Feng, "On Bounding the Minimum Distance of Cyclic Codes," in proceedings of the Int. Symp. on Information Theory, ISIT, Kobe, Japan, June 1988.